The invention relates to a field plate trench transistor.
Field plate trench transistors are normally designed such that they have a specific turned-on resistance Ron·A (Ron=Turned-on resistance; A=cross-sectional area of the drift zone) which is as low as possible. In addition, to minimize switching losses and to reduce the driver power of the gate actuation, the quantity of charge QG (“gate charge”) which needs to flow to the gate electrode or to drain from it in order to switch the transistor between off state/on state should be as small as possible. The required quantity of charge QG can be relatively large both in the case of standard trench transistors (UMOS) and in the case of field plate trench transistors, which have a small pitch (width of an active cell within the cell array) and which are designed for high voltages, and can therefore entail the aforementioned drawbacks.
FIG. 1 shows a field plate trench transistor which requires a smaller quantity of charge QG in comparison with conventional field plate trench transistors.
The field plate trench transistor 1 has a drain contact 2, a semiconductor body 3 arranged on the drain contact 2, and a source contact 4 arranged on the semiconductor body 3. The semiconductor body 3 has an n+-doped drain connection region 5, an n−-doped drift region 6 arranged on the drain connection region 5, and a p-doped body region 7 arranged on the drift region 6. The body region 7 contains n+-doped source regions 8. The semiconductor body 3 also contains trenches 9 whose inner walls are lined with an insulating layer 10 whose thickness may vary depending on the depth of the trench. In this case, a thinner insulating layer is used in the region of the body region 7 (channel region) than in the region of the drift region 6. Within the trenches 9, a gate electrode 11 and a field electrode 12 arranged below it are respectively formed. The gate electrode 11 is electrically insulated from the field electrode 12. In addition, the gate electrode 11 is electrically insulated from the source contact 4 by means of an insulating layer 13. The gate electrode 11 extends through the body region 7 and, in the on state, induces channels from the source regions 8 to the drift region 6 in the body region 7.
Unlike in standard trench transistors, the trenches 9 in the field plate trench transistor 1 extend entirely up to or close to the drain connection region 5. The clearing effect of the “extended” trenches allows the drift region 6 to be provided with a higher level of doping for a given breakdown voltage than in the case of a planar pn junction or a standard trench transistor. For an even higher reverse voltage, a further drift zone 61 whose doping level is lower than that of the drift region 62 may be provided below the trench 9.
The field electrodes 12 of the field plate transistor 1 are at source potential, and the gate electrodes 11 are at gate potential, which has the effect that, in comparison with field plate transistors with just one electrode per trench, some of the gate/drain capacitance is converted into source/drain capacitance. This means that it is possible to lower the gate charge QG required for switching the transistor (charging/discharging the electrodes 11, 12), which entails a reduction in the switching losses and in the driver power.
In addition, U.S. Pat. No. 5,864,159 discloses a standard trench transistor (UMOS) which is shown in FIG. 7. The trench transistor has trenches 9 which, in contrast to the preceding field plate trench transistor embodiments, extend only just over the body region 7 into the drift region 6. Also, the insulating layer 10 is in a continuously thin form, that is to say has no thickened regions.
FIG. 8 shows a further known trench transistors 80. The difference from the embodiment shown in FIG. 1 is that in the two trenches 9 the gate and field electrodes are “fused” to form a common electrode 32 which is a gate potential.